1. Field of the Invention
The present invention relates to a method for testing digital logic circuits, and in particular for the dynamic testing of digital logic circuits in which a digital logic circuit is supplied by cyclically-occurring digital signals having a predetermined chronological spacing and in which an anticipated value is identified in all cycles of the digital signals at the outputs of the logic circuit as predicted from input signals applied to the inputs of the logic circuit and in which blank or dummy cycles are introduced after a predetermined number of test cycles and which have the character that modifications of the input signals no longer appear.
2. Description of the Prior Art
There are two things to be understood herein with respect to the term "dynamic testing of logic circuits".
During the development of a digital logic circuit, the behavior of a circuit is investigated with the assistance of a logic simulator and is tested for coincidence with a reference behavior under real-time conditions.
During manufacture, for example as an integrated circuit, each unit is tested with an automatic testing unit in that its behavior is tested for coincidence with an error-free circuit. Here, also, it is desirable to have the test sequence performed on a real-time basis.
A bit pattern is applied to the circuit in both instances and the reaction of the outputs is observed.
The application of the bit pattern occurs in a step-by-step process in accordance with a defined chronological sequence that must correspond to the operating frequency of the circuit.
The testing of the circuit occurs in that the states measured at the outputs in each of the testing steps at a defined strobe time are compared to anticipated reference values.
When these test steps are extremely short, this corresponding to a high-operating frequency, then the problem arises that the reaction of the outputs to the input modifications no longer occurs within the test step, but at a later time. An unambiguous allocation of an input bit pattern to an output bit pattern is then no longer possible.
In the case of manufacture, the additional problem also arises that output signals must be transmitted from the unit under test to a receiver portion of the automatic testing unit and must be processed there. As already mentioned above, an unambiguous allocation of an input bit pattern to an output bit pattern is therefore made additionally more difficult. It must thereby be taken into consideration that the available technology makes pattern generators available that can supply a logic circuit with input signals into the GHz range. Processing signals up to approximately 100 MHz, however, presents extreme difficulties at the receiver side.
A shift of the strobe time is extremely problematical since, dependent on the operating parameters, the delay times fluctuate greatly (worst case/best case&gt;6) or, respectively, the outputs to be evaluated do not have the same delay compared to one another.
The problem has heretofore been resolved in the development of logic circuits such that the circuit developer has observed the outputs as a pulse diagram with the assistance of the logic simulator and has visually compared the same to anticipated values.
Given the occurrence of the above-described problems of a great chronological delay between inputs and outputs, the designer either had to mentally compensate for this delay or he only looked for the proper sequence of the pulses in the output signals.
Since such a test must be repeatedly implemented during the development of a logic circuit, a procedure is desirable which, after a one-time, careful check of the function, allows the identified result to be stored in a computer and allows further tests to be automatically implemented by the computer.